Designing Digital Computer Systems with Verilog by David J. Lilja

By David J. Lilja

This ebook explains the right way to specify, layout, and try an entire electronic procedure utilizing Verilog.

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19 20 A Verilogical place to start 46. ‘S1: if (sword_sharpened) 47. next_state = ‘S2; 48. else 49. next_state = ‘S1; 50. ‘S2: if (courage) 51. if (dragon) 52. next_state = ‘S3; 53. else 54. next_state = ‘S2; 55. else 56. next_state = ‘S0; 57. ‘S3: if (dragon) 58. next_state = ‘S2; 59. else 60. next_state = ‘S4; 61. ‘S4: next_state = ‘S4; 62. default: $display(‘‘Illegal state’’); 63. endcase 64. end 65. 66. always @(posedge clock) // Updates the state at 67. present_state = next_state; // positive clock edge 68.

These bits are: • Carry bit – C: The C bit is set to 1 to indicate that a carry out has occurred from the most significant bit of an unsigned operation. It is set to 0 if no carry occurs. • Zero bit – Z: The Z bit is set to 1 if all of the bits in the result are 0. If at least a single bit is a 1, the Z bit is set to 0. Thus, this condition bit indicates that the arithmetic value of the result was zero. • Negative bit – N: This bit is set to 1 when the result is negative. A 0 value indicates that the result was positive or zero.

It thereby implicitly specifies the next instruction to be executed. With a PC, only branch and jump instructions need to explicitly specify the next instruction. 2 Defining the VeSPA instruction set The first step in defining the instruction set for a new processor is to select the set of instructions from each of the above categories that will produce a logically complete set. Additionally, we want the instructions in this set to be simple to implement, and we typically want the smallest number of instructions necessary to efficiently execute the application programs.

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